1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit used for protecting an integral circuit electrically connected to at least two power sources.
2. Description of the Prior Art
With the advancement of technology, the development of semiconductor processes is ongoing. A modern chip is allowed to have a plurality of various electronic circuits configured within. Recently, the chip of integrated circuit can be divided into a core circuit and an input/output (I/O) circuit, and the core circuit and the I/O circuit are respectively driven by different power sources with different voltages. In order to receive the external power sources by the core circuit and the I/O circuit, the chip of the integrated circuit has core power pads and I/O power pad disposed thereon.
However, during processes such as packaging, testing, delivering, and manufacturing, etc., the pads easily transfer electrostatic charges that are not suitable for the chip to the inner circuit in the chip, and further, the electrostatic charges damage the inner circuit in the chip. The unwanted condition causing the inner circuits of the chip to be damaged is called electrostatic discharge (ESD). Therefore, an ESD protection circuits used for protecting integrated circuit chip from being damaged by the unwanted ESD become more important with the advancement of the semiconductor processes.
Refer to FIG. 1, which is a circuit diagram illustrating an ESD protection circuit used for protecting an integrated circuit electrically connected to two power sources according to the prior art. As shown in FIG. 1, each power source 10 has a high power line 10a and a low power line 10b respectively. An ESD event may occur in each high power line 10a and each low power line 10b, and ESD current may flow toward other high power lines 10a and other low power lines 10b. In order to protect an integrated circuit electrically connected to the two power sources 10, the ESD protection circuit 12 of the prior art is electrically connected to the power sources 10, and includes four power clamp circuits 14 that are electrically connected between each high power line 10a and each low power line 10b respectively. Furthermore, each power clamp circuit 14 includes a capacitor 16, a resistor 18, a first n-type metal-oxide-semiconductor (NMOS) transistor 20, a second NMOS transistor 22, and a diode 24. Each capacitor 16 is electrically connected between the corresponding high power line 10a and a gate of each first NMOS transistor 20, and each resistor 18 is electrically connected between the corresponding low power line 10b and the gate of each first NMOS transistor 20. Accordingly, in each power clamp circuit 14, when the ESD event occurs in the high power line 10a, a RC circuit composed of the capacitor 16 and the resistor 18 can provide a high voltage potential to the gate of the first NMOS transistor 20 so as to turn on the first NMOS transistor 20. Furthermore, a drain and a source of each first NMOS transistor 20 are electrically connected to the corresponding high power line 10a and a body of each second NMOS transistor 22 respectively. When the first NMOS transistor 20 is turned on, electrostatic charges occurring in the high power line 10a can flow through the first NMOS transistor 20 to trigger on the second NMOS transistor 22, and the second NMOS transistor 22 is turned on. A drain and a source of each second NMOS transistor 22 are electrically connected to the corresponding high power line 10a and the corresponding low power line 10b respectively, and a gate of each second NMOS transistor 22 is electrically connected to the corresponding low power line 10b. When the second NMOS transistor 22 is turned on, the electrostatic charges occur in the high power line 10a can flow through the second NMOS transistor 22, and is introduced to the low power line 10b. Accordingly, the electrostatic charges in the high power line 10a can be introduced to the low power line 10b. Furthermore, an anode and a cathode of each diode 24 are electrically connected to the corresponding low power line 10b and the corresponding high power line 10a, so that an ESD event occurring in the low power line 10b can be introduced to the high power line 10a. 
As the above-mentioned description, each high power line 10a and each low power line 10b require a power clamp circuit 14 electrically connected between them to introduce the electrostatic charges occurring in each high power line 10a, and each power clamp circuit 14 require a capacitor 16 and a resistor 18 to be a detection circuit used for detecting the electrostatic charges occurring in each high power line 10a so as to provide high voltage potential to the gate of the first NMOS transistor 20. For this reason, when the number of the power sources is two, four power clamp circuits 14 are required to protect the integrated circuit electrically connected between the power sources. When the number of the power sources is added to be three, the number of the power clamp circuit 14 should be added to be nine, so that nine capacitors 16 and nine resistors 18 should be increased to be detection circuits. However, in the chip of the integrated circuit of the prior art, the capacitors 16 and the resistors 18 occupy a certain proportion of the area of the chip. Thus, when the chip of the integrated circuit requires more power sources 10, the number of the capacitor 16 and resistor 18 in the ESD protection circuit 12 is accordingly increased, and the size of the chip of the integrated circuit is limited by the capacitors 16 and the resistors 18.
Therefore, it is an important objective to reduce the number of the capacitor and the resistor in the ESD protection circuit.